First Experimental Demonstration of 3D-Stacked 2T0C DRAM Cells Based on Indium Tin Oxide Channel

作者：C.L. Gu, Qianlan Hu, Shenwu Zhu, Qijun Li, Min Zeng, Jiyang Kang, Anyu Tong, Yanqing Wu · 发表于：IEEE Electron Device Letters · 年份：2024 · DOI：10.1109/led.2024.3443512 · 被引用次数：27 · 研究领域：Advanced Memory and Neural Computing、Semiconductor materials and devices、Ferroelectric and Negative Capacitance Devices

In this letter, we provide the first experimental demonstration of 3D-stacked 2T0C DRAM cells based on indium tin oxide (ITO) FETs. The 3D sequential integration process steps cause negligible performance degradation to the bottom ITO FET including on-current, on/off ratio, subthreshold slope, and mobility, exhibiting excellent stability during the fabrication process of the top FET. Both layers of FETs show very small threshold voltage Vthshift under positive bias stress measurement for 3,000 s, where the negative shift of Vthis only about 0.045 V and 0.08 V for the 1stand 2ndlayer FETs, respectively. The 3D-stacked 2T0C DRAM cell consisting of two ITO FETs shows excellent data retention time of 1,360 s and endurance over 1011, rivaling the counterparts based on planar structures. These results indicate the great potential of the 3D-stacked 2T0C DRAM cells for future 3D DRAM applications.