An innovative hybrid full adder design for low-power VLSI circuit applications

作者：Aman Sharma, Nitin Singha, Rajendra Yadav, Ashish Kumar · 年份：2024 · DOI：10.1201/9781032644752-69 · 被引用次数：2 · 研究领域：Low-power high-performance VLSI design、Quantum-Dot Cellular Automata、Quantum Computing Algorithms and Architecture

This research introduces an innovative Hybrid Full Adder (HFA) configuration integrating Pass Transistor Logic (PTL), Complementary Metal-Oxide-Semiconductor (CMOS) logic, and transmission gate (TG) logic within the framework of 90-nanometer technology. The HFA is composed of several modules, including EX-OR, carry generator, and sum generator, with an additional inverter logic to achieve the necessary EX-NOR functionality. The proposed HFA exhibits impressive performance with a propagation delay of 19.091 ns and an average power consumption of approximately 5.759 μW at a 1V supply voltage. The most noteworthy aspect is its remarkably low power delay product (PDP) of 139.12 fJ, demonstrating excellent power efficiency. Moreover, the proposed design utilizes only 13 transistors, resulting in a compact layout. The study suggests that this efficient HFA design can be a valuable building block for low-power VLSI circuits, offering significant improvements in power efficiency.