Study on Characteristics and UIS of Hexagonal Planar SiC VDMOSFETs With Varied JFET Width

作者：Houcai Luo, Huan Wu, Jingping Zhang, Bofeng Zheng, Lei Lang, Guoqi Zhang, Xianping Chen · 发表于：IEEE Transactions on Device and Materials Reliability · 年份：2024 · DOI：10.1109/tdmr.2024.3388482 · 被引用次数：7 · 研究领域：Silicon Carbide Semiconductor Technologies、Semiconductor materials and devices、Advancements in Semiconductor Devices and Circuit Design

The hexagonal cell topology of planar SiC VDMOSFETs with varied JFET width (LJFET) are designed and manufactured in this study. LJFET = 1.4μm has the best HF-FOM (Ron×Cgd) and HF-FOM (Ron×Qgd) by comparing the dynamic and static parameters of each design. Besides, the UIS reliability and failure mechanism for series designs are investigated by experiment and TCAD simulation. The results show that the high temperature is generated by energy dissipation during avalanche and it drives the parasitic BJT conduction, causing Ids out of control and instantaneous heat concentration in a very short time. The extremely high temperature causes internal cracking of the material and metal melting, resulting in gate-source short circuit and device damage. It would provide suggestions for device design and reliability consideration.