14.7 A 0.45V 0.72mW 2.4GHz Bias-Current-Free Fractional-N Hybrid PLL Using a Voltage-Mode Phase Interpolator in 28nm CMOS

作者：Liqun Feng, Xuansheng Ji, Longhao Kuang, Qianxian Liao, Han Su, Jiahao Zhao, Woogeun Rhee, Zhihua Wang · 年份：2024 · DOI：10.1109/isscc49657.2024.10454404 · 被引用次数：4 · 研究领域：Advancements in PLL and VCO Technologies、Semiconductor materials and devices、Photonic and Optical Devices

Low-voltage clock generation and modulation are important to have dynamic voltage scaling for low-power SoC design or to enable the chip to be directly powered by energy harvesters for IoT applications. Even though the supply voltage of an integer-N PLL has reached 0.4V [1], designing a robust fractional-N PLL under 0.5V is still challenging as both a high-performance phase detector (PD) and an effective ΔΣ quantization noise (Q-noise) reduction method are required at low voltage. As shown at the top of Fig. 14.7.1, the time resolution of a DTC is severely degraded as supply voltage decreases, and the use of a circuit’s intrinsic time delay as reference base is not stable over PVT variations. Even though voltage-domain compensation methods [2, 3] achieve lower noise and better linearity, they must first convert the phase error from the time domain to the voltage domain, which causes nonlinearity issues and consumes significant voltage headroom for ultra-low-voltage (ULV) operations. To the best of authors’ knowledge, the lowest supply voltage for a published fractional-N PLL is 0.5V, but it uses an on-chip voltage booster to supply a higher internal voltage for the TDC [4] or must use large decoupling capacitors for the TDC in product-level designs. Given the fact that the use of a large decoupling capacitor with supply regulation is required in practice to achieve robust in-band noise performance, a time-interleaving flip-flop phase detector (TI-FFPD) has been proposed as an...