Efficient Approximate Floating-Point Multiplier With Runtime Reconfigurable Frequency and Precision

作者：Zhenhao Li, Zhaojun Lu, Wei Jia, Runze Yu, Haichun Zhang, Gefei Zhou, Zhenglin Liu, Gang Qu · 发表于：IEEE Transactions on Circuits & Systems II Express Briefs · 年份：2024 · DOI：10.1109/tcsii.2024.3364717 · 被引用次数：7 · 研究领域：Low-power high-performance VLSI design、Numerical Methods and Algorithms、Parallel Computing and Optimization Techniques

Deep Neural Networks (DNNs) perform intensive matrix multiplications but can tolerate inaccurate intermediate results to some degree. This makes them a perfect target for energy reduction by approximate computing. However, current research in this direction requires DNNs redesign and does not provide the flexibility for users to trade accuracy for energy saving. In this paper, we propose a runtime reconfigurable approximate floating-point multiplier and present details of its hardware implementation. The flexible computation precision is provided by our error correction module, which is controlled by reconfigurable clock signals. The circuit design solves the glitch and metastability problems. The proposed approximate multiplier with three precision levels is evaluated on Synopsys design compiler and Xilinx FPGA platforms. Experimental results demonstrate the advantages of our approach in terms of speed, hardware overhead, and power consumption, while ensuring a controllable accuracy loss for DNNs inferences.