A 40-nm 1.89-pJ/SOP Scalable Convolutional Spiking Neural Network Learning Core With On-Chip Spatiotemporal Back-Propagation

作者：Pai-Yu Tan, Cheng‐Wen Wu · 发表于：IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 年份：2023 · DOI：10.1109/tvlsi.2023.3327417 · 被引用次数：19 · 研究领域：Advanced Memory and Neural Computing、Ferroelectric and Negative Capacitance Devices、Neural Networks and Reservoir Computing

In recent years, progress in spiking neural network (SNN) research has generated growing interest in specialized SNN hardware. However, most of the hardware studies are about inference-only engines, and the training process for low-power endpoint devices remains arduous due to high numerical precision requirements. In this article, we introduce a scalable convolutional SNN learning core for energy-efficient training utilizing the spatiotemporal back-propagation (STBP) algorithm. We modify the STBP algorithm with five hardware-based enhancing methods, which minimize the hardware implementation cost without losing accuracy. We propose a unified core architecture encompassing three data-flow modes for three training phases. It also offers multicore scalability for wider and deeper models. A 40-nm prototype chip has been implemented, achieving peak training and inference efficiencies of 3 and 7.7 TOPS/W, respectively, at 90% input sparsity and an energy per synaptic operation (SOP) metric of 1.89 pJ/SOP. Based on the chip, our multicore prototype system attains a competitive accuracy of 99.1% on MNIST. We also exhibit the first on-chip training results on SVHN and CIFAR10, with an average of$36\times $improvement in efficiency compared with a typical commercial GPU platform.