Power Prediction of RTL-Level Circuits by Using Machine Learning

作者：Jie Wang, Kang Li, Jiawei Chen, Ruizhi Shi, Liyun Chen, Weisheng Chen · 年份：2023 · DOI：10.1109/iseda59274.2023.10218595 · 被引用次数：6 · 研究领域：Low-power high-performance VLSI design、Interconnection Networks and Systems、Embedded Systems Design Techniques

This paper proposes a power prediction framework by using machine learning (ML), which extracts the Hamming distance of the signals from the VCD file generated by RTL simulation as the power features, and uses the power values after placement and routing as the labels. On the 100G network processor (NP) chip adopting 28nm process, the circuit components are divided and the key signals are selected. The power model based on RTL design is constructed, and the power consumption of the system is predicted based on the method of component superposition. The existing experimental results show that the prediction error of component level and system level is less than 15% as a whole, and less than 10% in most cases.