Comprehensive Analysis and Optimization of Parasitic Capacitance on Conducted EMI and Switching Losses in Hybrid-Packaged SiC Power Modules

作者：Yifan Zhang, Yue Xie, Cai Chen, Xinyue Guo, Yiyang Yan, Lei Yang, Yong Kang · 发表于：IEEE Transactions on Power Electronics · 年份：2023 · DOI：10.1109/tpel.2023.3306892 · 被引用次数：28 · 研究领域：Electromagnetic Compatibility and Noise Suppression、Silicon Carbide Semiconductor Technologies、Advanced DC-DC Converters

The high switching speeds of Wide BandGap (WBG) devices promise further breakthroughs in the development of power modules. However, parasitic parameters bring more adverse effects at high-speed switching conditions, which makes WBG bring more power loss and ElectroMagnetic Interference (EMI) problems. In this article, a 1200-V/24-A SiC half-bridge power module is presented with ultralow parasitic capacitance and inductance for low common-mode (CM) EMI and low power loss. This module is designed from a stacked substrate hybrid package structure by optimizing the layout pattern. The effects of parasitic capacitance on the switching loss and conducted EMI of SiC devices are comprehensively investigated based on the analysis models. And the parasitic capacitance reduction methods and the tradeoff optimization for geometrical parameters are given accordingly. The power module's layout is designed, optimized, and fabricated based on the analysis results. The proposed SiC half-bridge module reduces CM current by 17 dB and total switching loss by 28.5% compared to discrete devices. Experimental results validate the superior performance of the optimized module.