A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique

作者：Lin Wang, Yong Chen, Chao-Wei Yang, Xiaoteng Zhao, Pui‐In Mak, Franco Maloberti, Rui P. Martins · 发表于：IEEE Transactions on Circuits and Systems I Regular Papers · 年份：2023 · DOI：10.1109/tcsi.2023.3263963 · 被引用次数：12 · 研究领域：Advancements in PLL and VCO Technologies、Analog and Mixed-Signal Circuit Design、Radio Frequency Integrated Circuit Design

This paper reports a reference-less frequency- detector-less single-loop bang-bang clock and data recovery (BBCDR) circuit featuring wide frequency acquisition. We use a current-starved ring oscillator controlled by a 5-bit resistive digital-to-analog converter to maintain quarter-rate operation, supporting a capture range of 110.4%. By the virtue of a deliberate-current-mismatch charge pump pair, we form the single-sided capture scheme in the frequency detection characteristic, eliminating the power-hungry circuits in the high-speed clock and data paths. Employing a hybrid control circuit, the proposed BBCDR automates frequency acquisition and phase tracking in the overall 32 bands. Prototyped in a 65-nm CMOS, the BBCDR covers a wide data rate from 10.8 to 37.4 Gb/s, achieving an acquisition speed of 4.63 [(Gb/s)/$\mu \text{s}$] and an energy efficiency of 1.3 pJ/bit.