Viscoelastic Simulation of Stress and Warpage for Memory Chip 3D-Stacked Package

作者：Xiyou Wang, Sicheng Cao, Guangsheng Lu, Daoguo Yang · 发表于：Coatings · 年份：2022 · DOI：10.3390/coatings12121976 · 被引用次数：6 · 研究领域：Electronic Packaging and Soldering Technologies、3D IC and TSV technologies、Material Properties and Processing

Three-dimensional-stacked packaging technology is widely used in memory chip packaging, which can greatly increase the utilization ratio of the packaging area. However, problems with the reliability of 3D-stacked packaging are also becoming more and more serious. In this paper, first, a dynamic mechanical analyzer is used to obtain the EMC viscoelasticity parameters. Then, the influence trend of different factors, such as EMC, die bond material and chip, on the performance of the memory chip 3D-stacked packaging under a fixed temperature cyclic loading condition is explored by the FE method.