Comprehensive Analysis and Improvement Methods of Noise Immunity of Desat Protection for High Voltage SiC MOSFETs With High DV/DT

作者：Xingxuan Huang, Shiqi Ji, Cheng Nie, Dingrui Li, Min Lin, Leon M. Tolbert, Fred Wang, William Giewont · 发表于：IEEE Open Journal of Power Electronics · 年份：2021 · 被引用次数：26 · 研究领域：Silicon Carbide Semiconductor Technologies、HVDC Systems and Fault Protection、Electromagnetic Compatibility and Noise Suppression

This paper comprehensively analyzes desaturation (desat) protection for high voltage (>3.3 kV) silicon carbide (SiC) MOSFETs and especially how to build in noise immunity under highdv/dt. This study establishes a solid foundation for understanding the trade-offs between noise immunity and response speed of desat protection. Two implementations of the desat protection for high voltage SiC MOSFETs are examined, including desat protection based on discrete components and desat protection realized with a gate driver integrated circuit (IC). Both positivedv/dtand negativedv/dtare investigated. Analysis results show that the highdv/dtwith long duration caused by high voltage SiC MOSFETs’ switching results in strong noise interference in the desat protection circuitry. The impact of numerous influencing factors is investigated analytically, such as parasitic capacitances, parasitic inductance, damping resistance, and clamping impedance. Under high positivedv/dt, extremely small parasitic capacitances (dv/dtis also derived quantitatively to guide the noise immunity improvement. The noise immunity analysis results and noise immunity improvement methods are validated with simulation and experimental results obtained from a phase leg based on 10 kV/20 A SiC MOSFETs.