A 4T2R RRAM Bit Cell for Highly Parallel Ternary Content Addressable Memory

作者：Xuehong Wang, Linfang Wang, Wang Ye, Junjie An, Chunmeng Dou, Zuheng Wu, Xumeng Zhang, Jing Liu, Chenggao Zhang, Zhihong Yao, Zhaoan Yu, Tuo Shi, Chixiao Chen, Xiping Jiang, Meng‐Fan Chang, Qi Liu · 发表于：IEEE Transactions on Electron Devices · 年份：2021 · DOI：10.1109/ted.2021.3107497 · 被引用次数：31 · 研究领域：Advanced Memory and Neural Computing、Ferroelectric and Negative Capacitance Devices、Network Packet Processing and Optimization

In this work, we present a four-transistor-two-resistor (4T2R) ternary content addressable memory (TCAM) bit cell based on the resistive memory (RRAM), comprising the conventional two-transistor-two-resistor (2T2R) cell with two additional comparison transistors. It can effectively amplify the match-line signal ratio (ML-ratio), lower the leakage current of the match cell (${I}_{{\mathrm {MATCH}}}$), and suppress the read disturbance. The proposed concept is silicon verified using the 180 nm CMOS technology with transition-metal-oxide (TMO) RRAM integrated at the back-end-of-line (BEOL). It achieves a considerable ML-ratio of 1860 and a low${I}_{{\mathrm {MATCH}}}$of 11.15 nA on average. In a typical search operation, it shows a negligible ML drop at the match case and a large ML swing range at the mismatch case. The SPICE simulation results further show it can support a long word-length (WDL) of 256 under a clock rate of 100 MHz for search operations, which demonstrates its promise for highly parallel nonvolatile TCAM.