A 10.8 µW Neural Signal Recorder and Processor With Unsupervised Analog Classifier for Spike Sorting

作者：Han Hao, Jiahe Chen, Andrew G. Richardson, Jan Van der Spiegel, Firooz Aflatouni · 发表于：IEEE Transactions on Biomedical Circuits and Systems · 年份：2021 · DOI：10.1109/tbcas.2021.3076147 · 被引用次数：34 · 研究领域：Advanced Memory and Neural Computing、Neuroscience and Neural Engineering、EEG and Brain-Computer Interfaces

Implantable brain machine interfaces for treatment of neurological disorders require on-chip, real-time signal processing of action potentials (spikes). In this work, we present the first spike sorting SoC with integrated neural recording front-end and analog unsupervised classifier. The event-driven, low power spike sorter features a novel hardware-optimized, K-means based algorithm that effectively eliminates duplicate clusters and is implemented using a novel clockless and ADC-less analog architecture. The 1.4mm2chip is fabricated in a 180-nm CMOS SOI process. The analog front-end achieves a 3.3 μVrmsnoise floor over the spike bandwidth (400 - 5000 Hz) and consumes 6.42 μW from a 1.5 V supply. The analog spike sorter consumes 4.35 μW and achieves 93.2% classification accuracy on a widely used synthetic test dataset. In addition, higher than 93% agreement between the chip classification result and that of a standard spike sorting software is observed using pre-recorded real neural signals. Simulations of the implemented spike sorter show robust performance under process-voltage-temperature variations.