Accelerator Integration for Open-Source SoC Design

作者：Davide Giri, Kuan-Lin Chiu, Guy Eichler, Paolo Mantovani, Luca P. Carloni · 发表于：IEEE Micro · 年份：2021 · DOI：10.1109/mm.2021.3073893 · 被引用次数：26 · 研究领域：Embedded Systems Design Techniques、Parallel Computing and Optimization Techniques、VLSI and Analog Circuit Testing

The open-source hardware community contributes a variety of processors and accelerators, but combining them effectively into a complete System-on-Chip (SoC) remains a difficult task. We present a design flow for the seamless hardware and software integration of accelerators into a complete SoC and for its evaluation through rapid FPGA-based prototyping. By leveraging ESP, our open-source platform for agile heterogeneous SoC design, we demonstrate FPGA prototypes of various SoC designs, featuring the NVIDIA Deep Learning Accelerator and the Ariane RISC-V 64-bit processor core.