Investigation of process variation in vertically stacked gate-all-around nanowire transistor and SRAM circuit

作者：Yabin Sun, Xianglong Li, Yue Zhuo, Yun Liu, Teng Wang, Xiaojin Li, Yanling Shi, Jun Xu, Liu Ziyu · 发表于：Semiconductor Science and Technology · 年份：2021 · DOI：10.1088/1361-6641/abe01b · 被引用次数：10 · 研究领域：Advancements in Semiconductor Devices and Circuit Design、Semiconductor materials and devices、Integrated Circuits and Semiconductor Failure Analysis

Abstract An investigation into the intrinsic process variations including random dopant fluctuation (RDF), interface trap fluctuation, work-function variation (WFV) and oxide thickness variation was undertaken in a vertically stacked gate-all-around nanowire transistor. The fluctuation of the electrical characteristics induced by different sources of variation was discussed. The impact of process variations on static random access memory (SRAM) was also studied. On-state current I ON could be affected by RDF in the source and drain region and the standard deviation can reach 17.2% of the median. WFV can cause obvious fluctuations in threshold voltage V TH and consequently in the read static noise margin (RSNM) of SRAM. It has been discovered that the RSNM was deteriorated by 6.8% by WFV, which causes great uncertainty among all variation sources.