Design Technology Co-Optimization for 3 nm Gate-All-Around Nanosheet FETs

作者：Meng Wang, Yabin Sun, Xiaojin Li, Yanling Shi, Shaojian Hu, Enming Shang, Shoumian Chen · 年份：2020 · DOI：10.1109/icsict49897.2020.9278197 · 被引用次数：11 · 研究领域：Advancements in Semiconductor Devices and Circuit Design、Semiconductor materials and devices、Nanowire Synthesis and Applications

In this work, an improved TCAD based Design Technology Co-Optimization (DTCO) is proposed for gate-all-around (GAA) Nanosheet FET (NSFET) at 3 nm technology node. Based on conventional DTCO, only an additional procedure is introduced to extract the SPICE model, while the huge computational expense in the TCAD simulation is saved. Compared to the 5 nm technology node, the performance of ring oscillator (RO) in the optimized 3 nm technology node increases by 30%, while the power decreases by 56%. Besides, dual-k spacer design for NSFETs at the device and circuit levels are also investigated.