Memristor-Based HTM Spatial Pooler With On-Device Learning for Pattern Recognition

作者：Xiaoyang Liu, Yi Huang, Zhigang Zeng, Donald C. Wunsch · 发表于：IEEE Transactions on Systems Man and Cybernetics Systems · 年份：2020 · DOI：10.1109/tsmc.2020.3035612 · 被引用次数：32 · 研究领域：Advanced Memory and Neural Computing、Neural dynamics and brain function、Neuroscience and Neural Engineering

This article investigates hardware implementation of hierarchical temporal memory (HTM), a brain-inspired machine learning algorithm that mimics the key functions of the neocortex and is applicable to many machine learning tasks. Spatial pooler (SP) is one of the main parts of HTM, designed to learn the spatial information and obtain the sparse distributed representations (SDRs) of input patterns. The other part is temporal memory (TM) which aims to learn the temporal information of inputs. The memristor, which is an appropriate synapse emulator for neuromorphic systems, can be used as the synapse in SP and TM circuits. In this article, a memristor-based SP (MSP) circuit structure is designed to accelerate the execution of the SP algorithm. The presented MSP has properties of modeling both the synaptic permanence and the synaptic connection state within a single synapse, and on-device and parallel learning. Simulation results of statistic metrics and classification tasks on several real-world datasets substantiate the validity of MSP.