Investigation on Short-Circuit Characterization and Optimization of 3.3-kV SiC MOSFETs

作者：Ximing Chen, Hong Chen, Bangbing Shi, Yafei Wang, Xuan Li, Cai-Neng Zhou, Chenzhan Li, Xiaochuan Deng, Haihui Luo, Yudong Wu, Bo Zhang · 发表于：IEEE Transactions on Electron Devices · 年份：2020 · DOI：10.1109/ted.2020.3037262 · 被引用次数：27 · 研究领域：Silicon Carbide Semiconductor Technologies、HVDC Systems and Fault Protection、Semiconductor materials and devices

The short-circuit (SC) ruggedness of 3.3-kV silicon carbide (SiC) MOSFETs is of great importance for traction applications. In this article, the SC characterization and failure mechanism of 3.3-kV planar-gate SiC MOSFETs are systematically studied by experiments and simulations. The measured SC withstanding time (SCWT) of 3.3-kV SiC MOSFETs is about 17 μs, and the SC energy density is 15.5 J/cm2. Research demonstrates that the current clamping phenomenon is attributed to the high density of interface traps (Dit) in the gate oxide of 3.3-kV SiC MOSFETs. Furthermore, the positive temperature feedback mechanism and the triggering of parasitic n-p-n transistor are proved to cause the SC failure. At last, three optimized cell structures are proposed for improving the SC capability of 3.3-kV SiC MOSFETs, where the optimal SCWT is enhanced by 23% without degrading the forward conduction capability.