Opportunities in Device Scaling for 3-nm Node and Beyond: FinFET Versus GAA-FET Versus UFET

作者：Uttam Kumar Das, Tarun Kanti Bhattacharyya · 发表于：IEEE Transactions on Electron Devices · 年份：2020 · DOI：10.1109/ted.2020.2987139 · 被引用次数：143 · 研究领域：Semiconductor materials and devices、Advancements in Semiconductor Devices and Circuit Design、Ferroelectric and Negative Capacitance Devices

The performances of FinFET, gate-all-around (GAA) nanowire/nanosheet,and U-shaped FETs (UFETs) are studied targeting the 3-nm node (N3) and beyond CMOS dimensions. To accommodate a contacted gate pitch (CGP) of 32 nm and below, the gate length is scaled down to 14 nm and beyond. While going from 5-nm node (N5) to 3-nm node (N3) dimensions, the GAA-lateral nanosheet (LNS) shows 8% reduction in the effective drain current (Ieff) due to an enormous rise in short channel effects, such as subthreshold slope (SS) and drain-induced barrier lowering (DIBL). On the other hand, 5-nm diameter-based lateral nanowire shows an 80% rise in total current driving capability (Ieff). Therefore, to enable future devices, we explored electrostatics and effective drive current (Ieff) in FinFET, GAA-FET, and UFET architectures at a scaled dimension. The performances of both Siand SiGe-based transistors are compared using an advanced device simulator, TCAD Sentaurus.