A Case Study of Testing Strategy for AI SoC

作者：Haiying Ma, Rui Guo, Quan Jing, Jing Han, Yu Huang, Rahul Singhal, Yang Wu, Xin Wen, Fanjin Meng · 年份：2019 · DOI：10.1109/itc-asia.2019.00024 · 被引用次数：18 · 研究领域：VLSI and Analog Circuit Testing、Integrated Circuits and Semiconductor Failure Analysis、Radiation Effects in Electronics

Recent advances in artificial intelligence (AI) are becoming a driving force behind the technological revolution and industrial transformation leading to economic and social development. Application specific AI SoCs are being developed at different companies to accelerate processing of the data-intensive AI computations. There are many new challenges in designing and implementing Design-For-Test (DFT) logic for AI SoCs. In this paper, we share our experiences with DFT implementation for our AI SoC. To achieve lower power and higher bandwidth for AI SoC, we use high speed Serdes PHY with lower threshold voltage, which uses many SoC pins. Therefore, it has a negative impact on DFT and ATPG due to lack of reusable IOs that can be used as scan test channels. In this paper, we present our solution and tradeoffs made to optimize DFT silicon area overhead, test cost, test coverage, pre-silicon verification run time with ready-to-use silicon bring-up methodologies.