The First Compact Model to Determine $V_{T}$ Distribution for DG-FinFET Due to LER

作者：Amita Amita, S. Mittal, Udayan Ganguly · 发表于：IEEE Transactions on Electron Devices · 年份：2018 · DOI：10.1109/ted.2018.2870282 · 被引用次数：10 · 研究领域：Advancements in Semiconductor Devices and Circuit Design、Semiconductor materials and devices、Integrated Circuits and Semiconductor Failure Analysis

We report the first compact model to estimate the${V}_{T}$distribution of double gate-FinFET due to line edge roughness. We derive closed-form expressions, representing the compact model, for: 1) mean and standard deviation of fin width (${W}_{\text {fin}}$) in terms of geometrical and variability parameters of the FinFET; 2)${V}_{T}$as a function of${W}_{\mathrm {fin}}$for uniform width fins; and 3)${V}_{T}$in tapered fins using percolation. The${V}_{T}$distribution produced from the compact model shows a good match with well-calibrated TCAD data and demonstrates an excellent accuracy (~3mV rms error) for a wide range of scaling and variability parameters. The model is simple, platform independent, and$\sim {\text {10}}^{\text {4}}{\times }$faster compared to TCAD. It enables intuitive understanding of design space for FinFET on the one hand, and accurate FinFET variability-aware circuits and system design on the other hand.