Numerical Investigation of High-Voltage Partial Buried P/N-Layer SOI LDMOS

作者：Yue Hu, Yanfei Gong, Huazhen Liu, Qianqian Xu, Wen‐Sheng Zhao, Jing Wang, Ying Wang, Gaofeng Wang · 发表于：IEEE Transactions on Electron Devices · 年份：2017 · DOI：10.1109/ted.2017.2724921 · 被引用次数：11 · 研究领域：Silicon Carbide Semiconductor Technologies、Semiconductor materials and devices、Advancements in Semiconductor Devices and Circuit Design

High-voltage lateral double-diffused MOSFETs with partial buried P/N-type silicon layers (PBPL/PBNL) in silicon-on-insulator(SOI) technology are investigated numerically. In the lateral direction, the partial buried silicon layer (PBL) can introduce an additional electric field peak, which improves the surface electric field distribution and increases the charge accommodation in the drift region. Consequently, in the vertical direction, PBPL and PBNL can both induce higher electric field into the buried-oxide layer, and thus enhance the breakdown voltage (BV) significantly. Due to the higher electron concentration in the drift region, the ON-resistance (RON) can be also reduced remarkably. The 2-D simulation results show that PBPL and PBNL SOIs can achieve BVs of 296 and 365 V, respectively, in comparison to the conventional SOI (BV ~ 225 V) and the buried N-layer SOI (BV ~ 231 V). In addition, by comparison with the conventional SOI, RON can be reduced about 31.7% and 13.8% for PBPL and PBNL SOIs, respectively. Finally, hybrid PBPL/PBNL SOIs are studied and shown to be capable of further improving the device performance.