Balancing of Peak Currents Between Paralleled SiC MOSFETs by Drive-Source Resistors and Coupled Power-Source Inductors

作者：Yincan Mao, Zichen Miao, Chiming Wang, Khai D. T. Ngo · 发表于：IEEE Transactions on Industrial Electronics · 年份：2017 · DOI：10.1109/tie.2017.2716868 · 被引用次数：110 · 研究领域：Silicon Carbide Semiconductor Technologies、Semiconductor materials and devices、Advancements in Semiconductor Devices and Circuit Design

The peak currents between two paralleled SiC MOSFETs could differ significantly due to the mismatch in threshold voltages Vth. The method described herein employs passive compensation (drive-source resistors and coupled power-source inductors) to balance the peak currents using one gate driver, no sensors, and no feedback- without increasing total switching loss when equivalent gate-drive resistance (Rg+ 0.5Rk) is kept constant. This solution works for both polarities of Vthmismatch and forces balancing from the first current peak. The extra voltage stress from this solution is mitigated by negative coupling. The passive components (resistance, self-inductance, and mutual inductance) are determined by an equation involving the magnitude of Vthmismatch, current rise time, and unbalance percentage. The influence of other parasitic inductances on current sharing is analyzed. The robustness of this passive balancing method is experimentally verified by a prototype with a significant amount of parasitic inductances. Test results show that the difference of peak currents can be reduced from 15% to 3% without changing the switching loss and voltage stress.