Advanced Fabrication Processes for Superconducting Very Large Scale Integrated Circuits

作者：Sergey Tolpygo, Vladimir Bolkhovsky, Terence Weir, Alex Wynn, Daniel Oates, Leonard Johnson, Mark Gouker · 发表于：IEEE Transactions on Applied Superconductivity · 年份：2016 · DOI：10.1109/tasc.2016.2519388 · 被引用次数：251 · 研究领域：Physics of Superconductivity and Magnetism、Superconducting and THz Device Technology、Surface and Thin Film Phenomena

We review the salient features of two advanced nodes of an 8-Nb-layer fully planarized process developed recently at MIT Lincoln Laboratory for fabricating single flux quantum (SFQ) digital circuits with very large-scale integration on 200-mm wafers: the SFQ4ee and SFQ5ee nodes, where “ee” denotes that the process is tuned for energy-efficient SFQ circuits. The former has eight superconducting layers with 0.5-μm minimum feature size and a 2-Ω/sq Mo layer for circuit resistors. The latter has nine superconducting layers: eight Nb wiring layers with the minimum feature size of 350 nm and a thin superconducting MoNxlayer (Tc~ 7.5 K) with high kinetic inductance (about 8 pH/sq) for forming compact inductors. A nonsuperconducting (Tcxlayer with lower nitrogen content is used for 6-Ω/sq planar resistors for shunting and biasing of Josephson junctions (JJs). Another resistive layer is added to form interlayer sandwich-type resistors of milliohm range for releasing unwanted flux quanta from superconducting loops of logic cells. Both process nodes use Au/Pt/Ti contact metallization for chip packaging. The technology utilizes one layer of Nb/AlOx-Al/Nb JJs with critical current density Jcof 100 μA/μm2and minimum diameter of 700 nm. Circuit patterns are defined by 248-nm photolithography and high-density plasma etching. All circuit layers are fully planarized using chemical mechanical planarization of SiO2interlayer dielectric. The following results and topics are presented and discusse...