Sub-50 nm P-channel FinFET

作者：Xuejue Huang, Wen‐Chin Lee, C. Kuo, Digh Hisamoto, Leland Chang, Jakub T. Kedzierski, Erik Anderson, Hideki Takeuchi, Yang‐Kyu Choi, Kuniji ASANO, Vivek Subramanian, Tsu-Jae King, Jeffrey Bokor, Chenming Calvin Hu · 发表于：IEEE Transactions on Electron Devices · 年份：2001 · DOI：10.1109/16.918235 · 被引用次数：287 · 研究领域：Advancements in Semiconductor Devices and Circuit Design、Semiconductor materials and devices、Silicon Carbide Semiconductor Technologies

High-performance PMOSFETs with sub-50-nm gate-length are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short-channel effects. This vertical double-gate SOI MOSFET features: 1) a transistor channel which is formed on the vertical surfaces of an ultrathin Si fin and controlled by gate electrodes formed on both sides of the fin; 2) two gates which are self-aligned to each other and to the source/drain (S/D) regions; 3) raised S/D regions; and 4) a short (50 nm) Si fin to maintain quasi-planar topology for ease of fabrication. The 45-nm gate-length p-channel FinFET showed an I/sub dsat/ of 820 /spl mu/A//spl mu/m at V/sub ds/=V/sub gs/=1.2 V and T/sub ox/=2.5 mm. Devices showed good performance down to a gate-length of 18 nm. Excellent short-channel behavior was observed. The fin thickness (corresponding to twice the body thickness) is found to be critical for suppressing the short-channel effects. Simulations indicate that the FinFET structure can work down to 10 nm gate length. Thus, the FinFET is a very promising structure for scaling CMOS beyond 50 nm.