Transistor design issues in integrating analog functions with high performance digital CMOS

作者：Amitava Chatterjee, K. Vasanth, D.T. Grider, M. Nandakumar, G. Pollack, Rahul Aggarwal, M. Rödder, H. Shichijo · 年份：1999 · DOI：10.1109/vlsit.1999.799386 · 被引用次数：55 · 研究领域：Semiconductor materials and devices、Advancements in Semiconductor Devices and Circuit Design、Advancements in Photolithography Techniques

Pocket or halo designs used in high performance digital CMOS design can degrade analog device performance. A new understanding of this phenomenon is presented using device simulation. The effect of pocket implant parameters on the trade-off between digital and analog performance is studied experimentally. Experimental data showing the beneficial effects of eliminating the pocket selectively from the drain end on analog performance is also shown.