A Three-Dimensional Stacked Fin-CMOS Technology for High-Density ULSI Circuits

作者：Xinjun Wu, Philip C. H. Chan, Shengdong Zhang, Chunhua Feng, Mansun Chan · 发表于：IEEE Transactions on Electron Devices · 年份：2005 · DOI：10.1109/ted.2005.854267 · 被引用次数：36 · 研究领域：Advancements in Semiconductor Devices and Circuit Design、Semiconductor materials and devices、Thin-Film Transistor Technologies

In this paper, a three-dimensional CMOS technology is proposed and implemented using stacked Fin-CMOS (SF-CMOS) architecture. The technology is based on a double layer silicon-on-insulator wafer formed by two oxygen implants to create two single-crystal silicon films with an oxide isolation layer in between. The proposed approach achieves a 50% area reduction and significant shortening of the wiring distance between active devices through vertical connection when compared with conventional planar CMOS technology. The SF-CMOS technology also inherits the scalability and two-dimensional processing compatibility of the FinFET structure. SF-CMOS devices and simple circuits were fabricated and characterized.