Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits

作者：Kaushik Roy, Subhas Chandra Mukhopadhyay, Hamid Mahmoodi · 发表于：Proceedings of the IEEE · 年份：2003 · DOI：10.1109/jproc.2002.808156 · 被引用次数：2363 · 研究领域：Semiconductor materials and devices、Advancements in Semiconductor Devices and Circuit Design、Low-power high-performance VLSI design

High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.