Next generation 650V CSTBTTM with improved SOA fabricated by an advanced thin wafer technology

作者：Ryu Kamibaba, Kazuya Konishi, Yusuke Fukada, Atsushi Narazaki, Masayoshi Tarutani · 年份：2015 · DOI：10.1109/ispsd.2015.7123381 · 被引用次数：22 · 研究领域：Silicon Carbide Semiconductor Technologies、Thin-Film Transistor Technologies、3D IC and TSV technologies

Using an advanced thin wafer technology, we have successfully fabricated the next generation 650V class IGBT with an improved SOA and maintaining the narrow distribution of the electrical characteristics for industrial applications. The applied techniques were the finer pattern transistor cell, the thin wafer process and the optimized back side doping concentration profiles. With the well organized back-side wafer process, the practically large chip has achieved without any sacrifice of the production yield. As a results, VCEsat-Eofftrade-off relationship and an Energy of Short Circuit by active Area (ESC/A) are improved in comparison with the conventional Punch Through (PT) structure.