A 0.1–5.0 GHz Reconfigurable Transmitter With Dual-Mode Power Amplifier and Digitally-Assisted Self-Calibration for Private Network Communications

作者：Yun Yin, Baoyong Chi, Yanqiang Gao, Xiaodong Liu, Zhihua Wang · 发表于：IEEE Transactions on Circuits and Systems I Regular Papers · 年份：2014 · DOI：10.1109/tcsi.2014.2334851 · 被引用次数：18 · 研究领域：Radio Frequency Integrated Circuit Design、Advanced Power Amplifier Design、Advancements in PLL and VCO Technologies

A 0.1-5.0 GHz 65 nm CMOS reconfigurable transmitter for private network wireless communications is presented. The transmitter integrates a 0.1-1.5 GHz high-efficiency dual-mode power amplifier to support low-cost narrowband applications and a 0.45-5.0 GHz efficiency-optimized pre-power amplifier to support high-performance wideband applications. A wideband PLL frequency synthesizer, DACs with reconfigurable sampling rate and the reconfigurable digital baseband processing with standard JESD207 interface are all included to implement the highly-integrated transmitter. Specifically, with the proposed digitally-assisted self-calibration technique for LO leakage and image rejection, the transmitter achieves 52 dBc LO leakage and >53 dBc image rejection ratio (IRR), showing 20 dB and 30 dB improvement compared with the un-calibrated cases, respectively. The system verifications have demonstrated an EVM of 1.7% for 905 MHz EDGE with 19.5 dBm output power, and an EVM of 3.2% for LTE Band42 with 5.5 dBm output power. This proposed transmitter has achieved the comparable or even better performance in linearity, noise floor and power consumption compared with the state-of-the-art reconfigurable transmitters.