A CMOS low-power multiple 2.5-3.125-Gb/s serial link macrocellfor high IO bandwidth network ICs

作者：Fuji Yang, J. O'Neill, Dave Inglis, J. Othmer · 发表于：IEEE Journal of Solid-State Circuits · 年份：2002 · DOI：10.1109/jssc.2002.804341 · 被引用次数：32 · 研究领域：Advancements in PLL and VCO Technologies、Radio Frequency Integrated Circuit Design、Photonic and Optical Devices

This paper presents an 8-channel 2.5-3.125-Gb/s/ch serial link transceiver that achieves a total IO bandwidth of 20 Gb/s with a power consumption of less than 685 mW. The macrocell uses a shared phase-locked loop (PLL) architecture to minimize the potential noise coupling from the core digital part. The clock recovery is based on a new four-quadrant analog phase interpolator to overcome the phase discontinuity in a traditional analog quadrature-phase mixing interpolator. A dynamic amplitude control algorithm is used to maintain the loop stability while maximizing the interpolator's output. The receiver is constructed using half-rate integrate-and-dump devices to eliminate the requirement of quadrature clock and to improve the receiver sensitivity. A PMOS transmitter driver is used, so that its output voltage referenced to the ground is independent of power supply voltage. On-chip clock generation PLLs are implemented to provide global half-rate clocks. The prototype chip fabricated in a 0.16-μm CMOS process is under a 1.5-V power supply. The measured recovered clock jitter is 87 ps, peak-to-peak. The transmitter's output jitter is 58 ps, peak-to-peak. The active area of the macrocell is about 2 mm2.