MOS Compatibility of high-conductivity TaSi2/n+poly-Si gates

作者：A. K. Sinha, W.S. Lindenberger, D. B. Fraser, Shyam P. Murarka, E.N. Fuls · 发表于：IEEE Transactions on Electron Devices · 年份：1980 · DOI：10.1109/t-ed.1980.20051 · 被引用次数：54 · 研究领域：Semiconductor materials and devices、Semiconductor materials and interfaces、Advancements in Semiconductor Devices and Circuit Design

The MOS-VLSI parameters and process compatibility of a high-conductivity refractory silicide gate with a sheet resistance of ∼ 2 Ω/□ have been evaluated. The gate metallization typically consisted of 2.5 kÅ TaSi2/2.5 kÅ poly-Si, which was sintered prior to patterning with a CF4/O2plasma etch. Measurements were made to determine the metal work function, oxide fixed charge, surface-states density, dielectric strength, oxide defect density, lifetime, current leakage, and the flat-band voltage stability with respect to mobile charge contamination, slow trapping, and hot-electron trapping. On IGFET's (500-Å SiO2, As-implanted source/ drain), VTand β measurements were made as a function of the back-gate bias and the channel length as small as 2 µm. The MOS and IGFET parameters are nearly ideal and correspond to those expected of n+poly-Si gates. Static and dynamic bias-temperature aging stability of the VFBis excellent. These characteristics are preserved through subsequent standard VLSI process steps. However, certain process and structure limitations do exist and these have been defined.