Three Dimensionally Stacked SiGe Nanowire Array and Gate-All-Around p-MOSFETs

作者：L. K. Bera, Hai Son Nguyen, Navaneet Kumar Singh, T. Y. Liow, Dandan Huang, Keat Mun Hoe, C. H. Tung, Weiwei Fang, S.C. Rustagi, Yu Jiang, G. Q. Lo, N. Balasubramanian, Dim‐Lee Kwong · 年份：2006 · DOI：10.1109/iedm.2006.346841 · 被引用次数：46 · 研究领域：Semiconductor materials and devices、Advancements in Semiconductor Devices and Circuit Design、Nanowire Synthesis and Applications

A novel method for realizing arrays of vertically stacked (e.g., times3 wires stacked) laterally spread out nanowires is presented for the first time using a fully Si-CMOS compatible process. The gate-all-around (GAA) MOSFET devices using these nanowire arrays show excellent performance in terms of near ideal sub-threshold slope (on/Ioffratio (~107), and low leakage current. Vertical stacking economizes on silicon estate and improves the on-state IDSATat the same time. Both n- and p-FET devices are demonstrated