Vertical Si-Nanowire $n$ -Type Tunneling FETs With Low Subthreshold Swing ( $\leq \hbox{50}\ \hbox{mV/decade}$ ) at Room Temperature

作者：Ramanathan Gandhi, Zhixian Chen, Navab Singh, Kaustav Banerjee, Sungjoo Lee · 发表于：IEEE Electron Device Letters · 年份：2011 · DOI：10.1109/led.2011.2106757 · 被引用次数：340 · 研究领域：Advancements in Semiconductor Devices and Circuit Design、Semiconductor materials and devices、Nanowire Synthesis and Applications

This letter presents a Si nanowire based tunneling field-effect transistor (TFET) using a CMOS-compatible vertical gate-all-around structure. By minimizing the thermal budget with low-temperature dopant-segregated silicidation for the source-side dopant activation, excellent TFET characteristics were obtained. We have demonstrated for the first time the lowest ever reported subthreshold swing (SS) of 30 mV/decade at room temperature. In addition, we reported a very convincing SS of 50 mV/decade for close to three decades of drain current. Moreover, our TFET device exhibits excellent characteristics without ambipolar behavior and with high Ion/Ioffratio (105), as well as low Drain-Induced Barrier Lowering of 70 mV/V.