A 1.5V 86mW/ch 8-channel 622-3125Mb/s/ch CMOS serdes macrocell with selectable MUX/DEMUX ratio

作者：Fuji Yang, J. O'Neill, P. Larsson, Dave Inglis, J. Othmer · 发表于：2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) · 年份：2005 · DOI：10.1109/isscc.2002.992103 · 被引用次数：11 · 研究领域：Advancements in PLL and VCO Technologies、Photonic and Optical Devices、Semiconductor Lasers and Optical Devices

An 8-channel serial link transceiver realizes 20 Gb/s full duplex total I/O throughput with <700 mW dissipation from a 1.5 V supply and occupies 2 mm/sup 2/ in 0.16 /spl mu/m CMOS. An analog DLL allows tracking of frequency offset up to 400 ppm. The receiver, employing an integrate-and-dump front-end, achieves 30 mVpp sensitivity.