A Phase Interpolator CDR with Low-Voltage CML Circuits

作者：Linan, Li -, Weipeng, Cai · 发表于：Acta Scientiarum Naturalium Universitatis Sunyatseni · 年份：2012 · 被引用次数：5 · 研究领域：Advancements in PLL and VCO Technologies、Parallel Computing and Optimization Techniques、Analog and Mixed-Signal Circuit Design

In this paper, a phase interpolator clock and data recovery (CDR) with low-voltage current mode logic (CML) latched, buffers, and muxes is presented. Because of using the CML circuits, the CDR can operate in a low supply voltage. And the original swing of the differential inputs and outputs is less than that of the CMOS logic. The power supply voltage is 1.2 V, and the static current consumption is about 20 mA. In this phase interpolator CDR, the charge pump and loop filter are replaced by a digital filter. And this structure offers the benefits of increased system stability and faster acquisition.