Maciej Ciesielski

机构：Poznań University of Technology · ORCID：0000-0002-3924-3638

发表论文 190 篇 · 总被引 2413 次 · h-index 25

代表论文

• Understanding Algebraic Rewriting for Arithmetic Circuit Verification: A Bit-Flow Model (2019 · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 被引 44)
• Functional Verification of Hardware Dividers using Algebraic Model (2019 · 被引 12)
• Formal Verification of Integer Dividers:Division by a Constant (2019 · 被引 8)
• Efficient Formal Verification and Debugging of Arithmetic Divider Circuits (2023 · 被引 5)
• Formal Verification of Restoring Dividers made Fast and Simple (2023 · 被引 4)
• Linear Algebra Approach to Verification of Modular $(2^{n}-1)$ Multipliers (2024 · 被引 3)